ARM, originally Acorn RISC Machine, later Advanced RISC Machine, is a family of reduced instruction set computing (RISC)architectures for computer processors, configured for various environments. British company ARM Holdings develops the architecture and licenses it to other companies, who design their own products that implement one of those architectures—including systems-on-chips (SoC) that incorporate memory, interfaces, radios, etc. It also designs cores that implement this instruction set and licenses these designs to a number of companies that incorporate those core designs into their own products.


Reduced instruction set computing, or RISC (pronounced ‘risk’), is a CPU design strategy based on the insight that a simplifiedinstruction set (as opposed to a complex set) provides higher performance when combined with a microprocessor architecture capable of executing those instructions using fewer microprocessor cycles per instruction. A computer based on this strategy is a reduced instruction set computer, also called RISC. The opposing architecture is called complex instruction set computing, i.e. CISC.

Various suggestions have been made regarding a precise definition of RISC, but the general concept is that of a system that uses a small, highly optimized set of instructions, rather than a more versatile set of instructions often found in other types of architectures. Another common trait is that RISC systems use the load/store architecture, where memory is normally accessed only through specific instructions, rather than accessed as part of other instructions like ADD.



Cortex-A Series Characteristics

Cortex-A processors are specifically designed to execute complex functions and applications such as those required by consumer devices like smartphones and tablets. Their performance efficiency is also making them an increasingly popular choice for servers and enterprise applications where large core clusters can be combined for optimal solutions.

In consumer electronics, Cortex-A processors are ideal for providing fast and immersive connected experiences. Their low-power architecture enables all-day browsing, connectivity, console-quality gaming, technologies such as NEON™ and support for the widest mobile app ecosystem. Across enterprise and networking solutions, Cortex-A processors enable highly scalable solutions to match performance requirements for more power-efficient package transfer, base stations, edge routers and servers.

All Cortex-A based processors share a commonly supported architecture and feature set, with each processor based on either the ARMv7-A or ARMv8-A architecture and feature set. The ARMv8-A architecture has a 64-bit execution state and can also support existing 32-bit applications. This backwards compatibility strengthens the 64-bit ecosystem. This commonality makes them the best solution for open platform design where compatibility and portability of software between designs is of upmost importance.

Cortex-A processors offer support for a rage of full Operating Systems including Linux, as well as others requiring a Memory Management Unit such as Android, Chrome and MontaVista.

Cortex-R Series Characteristics

Fundamental to the Cortex-R4, Cortex-R5, Cortex-R7, and Cortex-R8 processors are key features that are demanded by deeply embedded and real-time markets such as automotive safety, storage or wireless baseband, where high-performance, real-time, safe and cost-effective processing is required.

High performance: Rapid execution of complex code and DSP functionality

  • High performance, high clock-frequency, deeply pipelined micro-architecture
  • Dual-core multi-processing (AMP/SMP) configurations
  • Hardware SIMD instructions for very high performance DSP and media functions

Real-time: Deterministic operation to ensure responsiveness and high throughput

  • Fast, bounded and deterministic interrupt response
  • Tightly Coupled Memories (TCM) local to the processor for fast-responding code/data
  • Low-Latency Interrupt Mode (LLIM) to accelerate interrupt entry

Reliable: Detects errors and maintains system operation

  • User and privileged software operating modes with Memory Protection Unit (MPU)
  • ECC and parity error detection/correction for Level-1 memory system and buses
  • Dual-Core Lock-Step (DCLS) redundant core configurations


Cortex-M Series Characteristics

Energy efficiency Ease of use
  • Power efficient 32-bit processors
  • Support for sleep modes
  • Low power design with further optimization packs available
  • Low power consumption enables longer battery life
  • Instructions to support sleep modes
  • Program in C/C++, easy software reuse
  • Wide range of tools available
  • Standardize software framework (Cortex-M Software Interface Standard)
  • Free DSP library
High performance Feature rich
  • Leading MCU performance
  • Instructions for bit manipulation
  • Low interrupt latency
  • Powerful DSP extensions and optional hardware Floating Point Unit
  • Powerful Interrupt Control with NVIC
  • OS support features
  • Memory Protection Unit (MPU)
  • Comprehensive debug and reliability features
Ecosystem Reduced system size
  • Largest ecosystem in the industry
  • Several thousands of MCU catalog parts
  • Wide range of development suites
  • Wide range of middleware & RTOS
  • Low gate count
  • High code density reduces memory size
  • Smaller area reduces die cost
  • Smaller area reduces chip package size




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